VLSI design of BCH decoder in NAND flash controller

被引：0
|
作者：
机构：
[1] Zheng, Zhaoxia
[2] Ding, Mingpeng
[3] Zhong, Jianfu
[4] Li, Jicheng
来源：
Zheng, Z. (zxzheng@hust.edu.cn) | 1600年 / Huazhong University of Science and Technology卷 / 42期
关键词：
D O I：
10.13245/j.hust.140120
中图分类号：
学科分类号：
摘要：
引用
收藏
相关论文
共 50 条
  • [1] An Area Efficient Design of BCH Decoder for Multi-Channel NAND Flash Memories
    Wang Hongjun
    Ni Kai
    Wang Weineng
    Zhao Yi
    Wang Zongchao
    Ma Jianshe
    [J]. 2ND INTERNATIONAL SYMPOSIUM ON COMPUTER NETWORK AND MULTIMEDIA TECHNOLOGY (CNMT 2010), VOLS 1 AND 2, 2010, : 139 - 142
  • [2] A low complexity LDPC-BCH concatenated decoder for NAND flash memory
    Chen, Zhongjie
    Sha, Jin
    Zhang, Chuan
    Yan, Feng
    [J]. IEICE ELECTRONICS EXPRESS, 2018, 15 (11):
  • [3] VLSI Implementation of BCH Error Correction for Multilevel Cell NAND Flash Memory
    Choi, Hyojin
    Liu, Wei
    Sung, Wonyong
    [J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2010, 18 (05) : 843 - 847
  • [4] Design and optimization of adaptable BCH codecs for NAND flash memories
    Fabiano, M.
    Indaco, M.
    Di Carlo, S.
    Prinetto, P.
    [J]. MICROPROCESSORS AND MICROSYSTEMS, 2013, 37 (4-5) : 407 - 419
  • [5] Design and Implementation of a NAND Flash Controller in SoC
    Gong Xin
    Dai Zibin
    Li Wei
    Feng Lulu
    [J]. 2011 INTERNATIONAL CONFERENCE OF ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC), 2011,
  • [6] Concatenated BCH Codes for NAND Flash Memories
    Cho, Sung-gun
    Ha, Jeongseok
    [J]. 2012 IEEE INTERNATIONAL CONFERENCE ON COMMUNICATIONS (ICC), 2012, : 2611 - 2616
  • [7] Controller eases NAND-flash-drive design
    Levy, M
    [J]. EDN, 1996, 41 (24) : 30 - 30
  • [8] Hardware Design and Simulation Test for NAND Flash Controller
    Ran, Jiquan
    Guo, Lin
    Zhang, Sangang
    Ma, Jiezhong
    Zhai, Zhengjun
    Guo, Yangming
    [J]. Xibei Gongye Daxue Xuebao/Journal of Northwestern Polytechnical University, 2017, 35 (02): : 304 - 309
  • [9] Low-Cost, Low-Power and High-Throughput BCH Decoder for NAND Flash Memory
    Lee, Kijun
    Lim, Sejin
    Kim, Jaehong
    [J]. 2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012), 2012, : 413 - 415
  • [10] NAND flash memory controller design with software/hardware partition
    Shen, Hao
    Fu, Yuzhuo
    [J]. Jisuanji Gongcheng/Computer Engineering, 2004, 30 (24):
12345