Generic arithmetic units for high-performance FPGA designs

As PLD applications expand to include high-speed computing, the number of data types required grows commensurately. Current applications of programmable devices require operations on various integer, fixed-point, and floating-point precisions, in both real and complex (a+jb) formats. Moreover, simulating large, high-precision systems that include arithmetic units requires significant time. In this paper, we present a method of VHDL programming that addresses the growing number of data types and simulation time to allow for rapid development and simulation of mathematical-based hardware designs.