共 50 条
- [41] A 400 MFLOPS FFT PROCESSOR VLSI ARCHITECTURE IEICE TRANSACTIONS ON COMMUNICATIONS ELECTRONICS INFORMATION AND SYSTEMS, 1991, 74 (11): : 3845 - 3851
- [42] COMPUTATION ALGORITHM AND ARCHITECTURE OF A SUPERFAST FFT PROCESSOR MEASUREMENT TECHNIQUES USSR, 1992, 35 (01): : 19 - 24
- [43] VLSI ARCHITECTURE FOR PIPELINE FFT PROCESSOR. Systems and Computers in Japan, 1987, 18 (12): : 18 - 28
- [44] Computationally efficient fast algorithm and architecture for the IFFT/FFT in DMT/OFDM systems 1998 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS-SIPS 98: DESIGN AND IMPLEMENTATION, 1998, : 356 - 365
- [46] Study on the FPGA realization of a self-defined floating-point FFT/IFFT processor 2005, Chinese Institute of Electronics, Beijing, China (27):
- [47] Realization FFT/IFFT in FPGA PROCEEDINGS OF THE THIRD INTERNATIONAL SYMPOSIUM ON INSTRUMENTATION SCIENCE AND TECHNOLOGY, VOL 3, 2004, : 1211 - 1214
- [48] Scalable low power FFT/IFFT architecture with dynamic bit width configurability 2014 27TH INTERNATIONAL CONFERENCE ON VLSI DESIGN AND 2014 13TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS (VLSID 2014), 2014, : 359 - 364
- [49] IFFT/FFT core architecture with an identical stage structure for wireless LAN communications 2004 IEEE 5TH WORKSHOP ON SIGNAL PROCESSING ADVANCES IN WIRELESS COMMUNICATIONS, 2004, : 606 - 610
- [50] An Area Efficient FFT/IFFT Processor for MIMO-OFDM WLAN 802.11n JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 2009, 56 (01): : 59 - 68