Hardware implementation of two-level scheduling algorithm in μC/OS-II

Aiming at the problem that μC/OS-II does not support round-robin scheduling of the same priority task, a two-level hybrid task scheduling strategy was proposed. In the first level, by putting the task priority as criterion for task scheduling, a preemptive scheduling of different priority task was implemented. And in the second level, adopting time slice circulars scheduling strategy, round-robin scheduling of same priority task was implemented. The waiting list of tasks was designed by on-chip registers of FPGA and the ready list of tasks was designed by RAM of FPGA, and to implement time slice circulars scheduling, hardware circuit for finding successor of task was designed. The system adopted VHDL, and simulated by the software ISE10.1. The simulation results show that the hardware implementation of the system is well-worked. © 2016 SERSC.