Area-Efficient Barrett Modular Multiplication With Optimized Karatsuba Algorithm

被引:1
|
作者
Zhang, Bo [1 ]
Yan, Shoumeng [1 ]
机构
[1] Ant Grp Co Ltd, Comp Syst Lab, Ant Res, Hangzhou 310000, Peoples R China
关键词
Barrett modular multiplication (BMM); cryptosystem; Karatsuba algorithm; modular multiplication (MM);
D O I
10.1109/TCAD.2024.3415017
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This article presents an area-efficient Barrett modular multiplication (BMM) algorithm, facilitating the development of cryptosystems like fully homomorphic encryption. Instead of implementing three normal multiplications required by classic BMM, our proposed BMM introduces optimizations for multiplication AB, truncated multiplication & LeftFloor;AB/2(f)& RightFloor; , and modular multiplication (MM) AB mod 2(f). Taking the 4-term Karatsuba algorithm as an example, an N-bit multiplication AB can be decomposed into 9 (N/4) -bit multiplications. Our optimized approaches for truncated multiplication and MM require an area equivalent to only 6.5 (N/4) -bit multiplications when f approximate to N . Furthermore, our optimized Karatsuba multiplications introduce efficient (E, I) matrix pairs, circumventing area overhead from complex I matrices and sign extension in multiplication. We also employ encode algorithm to eliminate many additions needed in BMM and inside multiplications, significantly shortening critical path. Experimental results demonstrate the advantages of our proposed BMM in terms of throughput and area efficiency.
引用
收藏
页码:4626 / 4639
页数:14
相关论文
共 50 条
  • [21] Fast hardware of Booth-Barrett's modular multiplication for efficient cryptosystems
    Nedjah, N
    Mourelle, LD
    COMPUTER AND INFORMATION SCIENCES - ISCIS 2003, 2003, 2869 : 27 - 34
  • [22] An area-efficient design for modular inversion in GF(2m)
    Wang, Jian
    Jiang, Anping
    2006 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, 2006, : 1496 - +
  • [23] Area-Efficient Parallel Multiplication Units for CNN Accelerators With Output Channel Parallelization
    Tang, Song-Nien
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2023, 31 (03) : 406 - 410
  • [24] Area-Efficient Modular Reduction Structure and Memory Access Scheme for NTT
    Guo, Wenbo
    Li, Shuguo
    2021 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2021,
  • [25] Throughput/Area-efficient ECC Processor Using Montgomery Point Multiplication on FPGA
    Khan, Zia-Uddin-Ahamed
    Benaissa, Mohammed
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2015, 62 (11) : 1078 - 1082
  • [26] AEKA: FPGA Implementation of Area-Efficient Karatsuba Accelerator for Ring-Binary-LWE-based Lightweight PQC
    Bao, Tianyou
    He, Pengzhou
    Xie, Jiafeng
    Jacinto, H. S.
    2023 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE TECHNOLOGY, ICFPT, 2023, : 6 - 6
  • [27] AEKA: FPGA Implementation of Area-Efficient Karatsuba Accelerator for Ring-Binary-LWE-Based Lightweight PQC
    Bao, Tianyou
    He, Pengzhou
    Xie, Jiafeng
    Jacinto, H. S.
    ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS, 2024, 17 (02)
  • [28] Efficient digit-serial modular multiplication algorithm on FPGA
    Pan, Jeng-Shyang
    Song, Pengfei
    Yang, Chun-Sheng
    IET CIRCUITS DEVICES & SYSTEMS, 2018, 12 (05) : 662 - 668
  • [29] Efficient FPGA implementation of modular multiplication based on Montgomery algorithm
    Yang, Yatao
    Wu, Chao
    Li, Zichen
    Yang, Junming
    MICROPROCESSORS AND MICROSYSTEMS, 2016, 47 : 209 - 215
  • [30] Design of RSA crypto-coprocessor based on the Barrett's modular multiplication algorithm
    State Key Lab of ASIC and System, Fudan Univ., Shanghai 200433, China
    Xi Tong Cheng Yu Dian Zi Ji Shu/Syst Eng Electron, 2006, 6 (830-833):