A Low-Power Network-on-Chip Power-Gating Design with Bypass Mechanism

被引：0
|
作者：
Ouyang, Yiming [1 ]
Chen, Zhiyuan [1 ]
Xu, Dongyu [1 ]
Liang, Huaguo [1 ]
机构：
[1] School of Computing and Information, Hefei University of Technology, Hefei,230601, China
来源：
Dianzi Yu Xinxi Xuebao/Journal of Electronics and Information Technology | 2024年 / 46卷 / 08期
关键词：
15;
D O I：
10.11999/JEIT231257
中图分类号：
学科分类号：
摘要：
引用
收藏
页码：3436 / 3444
相关论文
共 50 条
  • [41] Dynamic Power Management with Power Network-on-Chip
    Vaisband, Inna
    Friedman, Eby G.
    2014 IEEE 12TH INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS), 2014, : 225 - 228
  • [42] Power Network-on-Chip for Scalable Power Delivery
    Vaisband, Inna
    Friedman, Eby G.
    2014 ACM/IEEE INTERNATIONAL WORKSHOP ON SYSTEM LEVEL INTERCONNECT PREDICTION (SLIP), 2014,
  • [43] An Energy-Efficient Virtual Channel Power-Gating Mechanism for On-Chip Networks
    Mirhosseini, Amirhossein
    Sadrosadati, Mohammad
    Fakhrzadehgan, Ali
    Modarressi, Mehdi
    Sarbazi-Azad, Hamid
    2015 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), 2015, : 1527 - 1532
  • [44] Low-power low-area network-on-chip architecture using adaptive electronic link buffers
    Sarathy, A.
    Kodi, A. K.
    Louri, A.
    ELECTRONICS LETTERS, 2008, 44 (08) : 512 - 513
  • [45] Low-power optical network-on-chip using low-loss multilayer silicon wire waveguide
    Jyoti Kedia
    Anurag Sharma
    Neena Gupta
    Journal of Optics, 2019, 48 : 557 - 566
  • [46] Low-power optical network-on-chip using low-loss multilayer silicon wire waveguide
    Kedia, Jyoti
    Sharma, Anurag
    Gupta, Neena
    JOURNAL OF OPTICS-INDIA, 2019, 48 (04): : 557 - 566
  • [47] Implementing a self-timed low-power java']java accelerator for network-on-chip applications
    Liang, Zheng
    Plosila, Juha
    Yan, Lu
    Sere, Kaisa
    SEVENTH INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED COMPUTING, APPLICATIONS AND TECHNOLOGIES, PROCEEDINGS, 2006, : 344 - +
  • [48] 3D floorplanning of low-power and area-efficient Network-on-Chip architecture
    Xue, Licheng
    Shi, Feng
    Ji, Weixing
    Khan, Haroon-Ur-Rashid
    MICROPROCESSORS AND MICROSYSTEMS, 2011, 35 (05) : 484 - 495
  • [49] Low power finite state machine synthesis using power-gating
    Pradhan, Sambhu Nath
    Kumar, M. Tilak
    Chattopadhyay, Santanu
    INTEGRATION-THE VLSI JOURNAL, 2011, 44 (03) : 175 - 184
  • [50] Power-gating aware floorplanning
    Jiang, Hailin
    Marek-Sadowska, Malgorzata
    ISQED 2007: PROCEEDINGS OF THE EIGHTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, 2007, : 853 - 858
12345