Design space exploration of neural network accelerator based on transfer learning

被引:0
|
作者
Wu Y. [1 ]
Zhi T. [2 ]
Song X. [2 ]
Li X. [1 ]
机构
[1] School of Computer Science, University of Science and Technology of China, Hefei
[2] State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences, Beijing
基金
中国国家自然科学基金;
关键词
design space exploration (DSE); multi-task learning; neural network accelerator; transfer learning;
D O I
10.3772/j.issn.1006-6748.2023.04.009
中图分类号
学科分类号
摘要
With the increasing demand of computational power in artificial intelligence (AI) algorithms, dedicated accelerators have become a necessity. However, the complexity of hardware architectures, vast design search space, and complex tasks of accelerators have posed significant challenges. Traditional search methods can become prohibitively slow if the search space continues to be expanded. A design space exploration (DSE) method is proposed based on transfer learning, which reduces the time for repeated training and uses multi-task models for different tasks on the same processor. The proposed method accurately predicts the latency and energy consumption associated with neural network accelerator design parameters, enabling faster identification of optimal outcomes compared with traditional methods. And compared with other DSE methods by using multilayer perceptron (MLP), the required training time is shorter. Comparative experiments with other methods demonstrate that the proposed method improves the efficiency of DSE without compromising the accuracy of the results. © 2023 Inst. of Scientific and Technical Information of China. All rights reserved.
引用
收藏
页码:416 / 426
页数:10
相关论文
共 50 条
  • [21] Design Space Exploration Scheme for Mapping Convolutional Neural Network on Zynq Zedboard
    Ul Hassan, M. Sohaib
    Khan, Umar S.
    Khawaja, Sajid Gul
    PROCEEDINGS OF THE 2020 12TH INTERNATIONAL CONFERENCE ON ELECTRONICS, COMPUTERS AND ARTIFICIAL INTELLIGENCE (ECAI-2020), 2020,
  • [22] An Artificial Neural Network Assisted Optimization System for Analog Design Space Exploration
    Li, Yaping
    Wang, Yong
    Li, Yusong
    Zhou, Ranran
    Lin, Zhaojun
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2020, 39 (10) : 2640 - 2653
  • [23] Neural-network based exploration in the discovery and design of materials
    Pao, YH
    Zhao, YL
    LeClair, SR
    Duan, BF
    ARTIFICIAL INTELLIGENCE IN REAL-TIME CONTROL 2000, 2001, : 43 - 48
  • [24] HierArch: A Cluster-Based DNN Accelerator with Hierarchical Buses for Design Space Exploration
    Huang, Jyun-Siou
    Chou, Ting-Han
    Lu, Juin-Ming
    Huang, Chih-Tsun
    Liou, Jing-Jia
    2023 IEEE 36TH INTERNATIONAL SYSTEM-ON-CHIP CONFERENCE, SOCC, 2023, : 313 - 318
  • [25] LCDSE: Enable Efficient Design Space Exploration for DCNN Accelerator Based on Layer Clustering
    Feng, Kaijie
    Fan, Xiaoya
    An, Jianfeng
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2024, 71 (10) : 4486 - 4490
  • [26] ACDSE: A Design Space Exploration Method for CNN Accelerator based on Adaptive Compression Mechanism
    Feng, Kaijie
    Fan, Xiaoya
    An, Jianfeng
    Li, Chuxi
    Di, Kaiyue
    Li, Jiangfei
    ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS, 2023, 22 (06)
  • [27] Design Space Exploration for Heterogenous SoC Integrated with Matrix Accelerator
    Wei, Jinghe
    Zhang, Ling
    Yu, ZongGuang
    Liu, De
    2020 IEEE 2ND INTERNATIONAL CONFERENCE ON CIRCUITS AND SYSTEMS (ICCS 2020), 2020, : 40 - 43
  • [28] Neural Network-Based Limiter with Transfer Learning
    Abgrall, Remi
    Han Veiga, Maria
    COMMUNICATIONS ON APPLIED MATHEMATICS AND COMPUTATION, 2020,
  • [29] Broadening the Exploration of the Accelerator Design Space in Embedded Scalable Platforms
    Piccolboni, Luca
    Mantovani, Paolo
    Di Guglielmo, Giuseppe
    Carloni, Luca P.
    2017 IEEE HIGH PERFORMANCE EXTREME COMPUTING CONFERENCE (HPEC), 2017,
  • [30] An aCCELERATOR-AWARE MICROARCHITECTURE SIMULATOR FOR DESIGN SPACE EXPLORATION
    Gao, Di
    Zhuo, Cheng
    2018 CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE (CSTIC), 2018,