Low-power scan testing for test data compression using a routing-driven scan architecture

被引：0

作者：

Xiang, Dong ^{[1
]}

Hu, Dianwei ^{[1
]}

Xu, Qiang ^{[2
]}

Orailoglu, Alex ^{[3
]}

机构：

[1] School of Software, Tsinghua University, Beijing 100084, China

[2] Department of Computer Science and Engineering, Chinese University of Hong Kong, Shatin, N.T., Hong Kong

[3] Department of Computer Science and Engineering, University of California, San Diego, La Jolla, CA 92093, United States

来源：

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2009年 / 28卷 / 01期

关键词：

Computer aided design - Flip flop circuits;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

A new scan architecture is proposed to reduce peak test power and capture power. Only a subset of scan flip-flops are activated to shift test data or capture test responses in any clock cycle. This can effectively reduce the capture test power and peak test power. Two routingdriven schemes are proposed to reduce the routing overhead. Experimental results show that the proposed scan architecture can effectively reduce peak test power, capture power, test data volume, and test application cost. © 2009 IEEE.

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页码：1101 / 1105

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