Experimental characterization of CMOS interconnect open defects

被引：0
|
作者：
IEEE [1 ]
不详 [2 ]
机构：
来源：
IEEE Trans Comput Aided Des Integr Circuits Syst | 1600年 / 1卷 / 123-136期
关键词：
D O I：
暂无
中图分类号：
学科分类号：
摘要：
Defects
引用
收藏
相关论文
共 50 条
  • [21] A Semi-analytical Model for Interconnect Open Defects in FinFET Logic Cells
    Forero, Freddy
    Galliere, Jean-Marc
    Renovell, Michel
    Champac, Victor
    2019 20TH IEEE LATIN AMERICAN TEST SYMPOSIUM (LATS), 2019,
  • [22] On testing of interconnect open defects in combinational logic circuits with stems of large fanout
    Reddy, SM
    Pomeranz, I
    Tang, HX
    Kajihara, S
    Kinoshita, K
    INTERNATIONAL TEST CONFERENCE 2002, PROCEEDINGS, 2002, : 83 - 89
  • [23] Multi-Cycle Circuit Parameter Independent ATPG for Interconnect Open Defects
    Erb, Dominik
    Scheibler, Karsten
    Sauer, Matthias
    Reddy, Sudhakar M.
    Becker, Bernd
    2015 IEEE 33RD VLSI TEST SYMPOSIUM (VTS), 2015,
  • [24] Voltage- and current-based fault simulation for interconnect open defects
    Konuk, H
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1999, 18 (12) : 1768 - 1779
  • [25] Experimental Verification of Single Event Interconnect Crosstalk in a 90 nm CMOS technology
    Balasubramanian, A.
    Amusan, O. A.
    Bhuva, B. L.
    Reed, R. A.
    Sternberg, A. L.
    Massengill, L. W.
    McMorrow, D.
    Nation, S. A.
    Melinger, J. S.
    RADECS 2007: PROCEEDINGS OF THE 9TH EUROPEAN CONFERENCE ON RADIATION AND ITS EFFECTS ON COMPONENTS AND SYSTEMS, 2007, : 238 - +
  • [26] INTERCONNECT DESIGN WITH VLSI CMOS
    SECHLER, RF
    IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 1995, 39 (1-2) : 23 - 31
  • [27] Resistance characterization for weak open defects
    Montañés, RR
    Volf, P
    de Gyuez, JP
    IEEE DESIGN & TEST OF COMPUTERS, 2002, 19 (05): : 18 - 26
  • [28] Experimental characterization of BTI defects
    Kaczer, B.
    Afanas'ev, V. V.
    Rott, K.
    Cerbu, F.
    Franco, J.
    Goes, W.
    Grasser, T.
    Madia, O.
    Nguyen, A. P. D.
    Stesmans, A.
    Reisinger, H.
    Toledano-Luque, M.
    Weckx, P.
    2013 18TH INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES (SISPAD 2013), 2013, : 444 - 450
  • [29] Diagnosis of resistive-open and stuck-open defects in digital CMOS ICs
    Li, JCM
    McCluskey, EJ
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2005, 24 (11) : 1748 - 1759
  • [30] Characterization of Interconnect Process Variation in CMOS Using Electrical Measurements and Field Solver
    Lim, Jun Jun
    Johari, Nor Adila
    Rustagi, Subhash C.
    Arora, Narain D.
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2014, 61 (05) : 1255 - 1261
12345