Trends in high-performance, low-power processor architectures

被引:0
|
作者
Murakami, Kazuaki [1 ]
Magoshi, Hidetaka [1 ]
机构
[1] Kyushu Univ, Fukuoka-shi, Japan
关键词
Computer architecture - Multimedia systems;
D O I
暂无
中图分类号
学科分类号
摘要
This paper briefly surveys architectural technologies of recent or future high-performance, low-power processors for improving the performance and power/energy consumption simultaneously. Achieving both high performance and low power at the same time imposes a lot of challenges on processor design, and therefore gives us a lot of opportunities for devising new technologies. The paper also tries to provide some insights into the technology, direction in future.
引用
收藏
页码:131 / 137
相关论文
共 50 条
  • [41] Issues and trends in high-performance processor cores
    Bose, P
    IEEE MICRO, 2003, 23 (02) : 5 - 5
  • [42] A high-performance low-power CMOS AGC for GPS application
    雷倩倩
    许奇明
    陈治明
    石寅
    林敏
    贾海珑
    Journal of Semiconductors, 2010, 31 (02) : 49 - 53
  • [43] Design of Low-Power High-Performance FinFET Standard Cells
    Wang, Tian
    Cui, Xiaoxin
    Liao, Kai
    Liao, Nan
    Yu, Dunshan
    Cui, Xiaole
    CIRCUITS SYSTEMS AND SIGNAL PROCESSING, 2018, 37 (05) : 1789 - 1806
  • [44] Custom Design in a Low-Power/High-Performance ASIC World
    Garibay, Ty
    Reis, Richard
    2009 IEEE INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUIT DESIGN AND TECHNOLOGY, PROCEEDINGS, 2009, : 1 - 2
  • [45] A high-performance,low-power ∑△ ADC for digital audio applications
    罗豪
    韩雁
    张泽松
    韩晓霞
    马绍宇
    应鹏
    朱大中
    Journal of Semiconductors, 2010, 31 (05) : 114 - 120
  • [46] High-Performance, Low-Power Resonant Clocking Embedded Tutorial
    Guthaus, Matthew R.
    Taskin, Baris
    2012 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD), 2012, : 742 - 745
  • [47] High-performance low-power sensing scheme for nanoscale SRAMs
    Valaee, A.
    Al-Khalili, A. J.
    IET COMPUTERS AND DIGITAL TECHNIQUES, 2012, 6 (06): : 406 - 413
  • [48] Optimization of Overdrive Signoff in High-Performance and Low-Power ICs
    Chan, Tuck-Boon
    Kahng, Andrew B.
    Li, Jiajia
    Nath, Siddhartha
    Park, Bongil
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2015, 23 (08) : 1552 - 1556
  • [49] LOW-POWER DESIGN TECHNIQUES FOR HIGH-PERFORMANCE CMOS ADDERS
    KO, UM
    BALSARA, PT
    LEE, W
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 1995, 3 (02) : 327 - 333
  • [50] A high-performance, low-power complementary coupled BiCMOS circuit
    Leung, WC
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1997, 32 (04) : 610 - 612