共 50 条
- [21] Formation and 3D Stacking Process of CMOS Chips with Backside Buried Metal Power Distribution Networks 2023 IEEE 73RD ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE, ECTC, 2023, : 1792 - 1797
- [22] Advances in 3D CMOS image sensors optical modeling: combining realistic morphologies with FDTD 2019 INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES (SISPAD 2019), 2019, : 351 - 354
- [23] Thinning, Stacking, and TSV Proximity Effects for Poly and High-K/Metal Gate CMOS Devices in an Advanced 3D Integration Process 2012 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2012,
- [24] Novel Chip Stacking Process for 3D Integration 2011 IEEE 61ST ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2011, : 1939 - 1943
- [25] Circuit and device technologies for CMOS functional image sensors IFIP VLSI-SOC 2006: IFIP WG 10.5 INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION & SYSTEM-ON-CHIP, 2006, : 42 - 47
- [27] New Technologies for advanced high density 3D packaging by using TSV process 2008 INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY & HIGH DENSITY PACKAGING, VOLS 1 AND 2, 2008, : 43 - 45
- [28] Advanced 1.1um Pixel CMOS Image Sensor with 3D Stacked Architecture 2014 SYMPOSIUM ON VLSI TECHNOLOGY (VLSI-TECHNOLOGY): DIGEST OF TECHNICAL PAPERS, 2014,
- [29] 3D integrated sensors in Silicon-on-Sapphire CMOS 2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS, 2006, : 4959 - +
- [30] Challenges and capabilities of 3D integration in CMOS imaging sensors 49TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE (ESSDERC 2019), 2019, : 54 - 56