共 50 条
- [1] Residues of Prime Numbers as Entries for the S-Box 2013 INTERNATIONAL CONFERENCE ON COMPUTING, ELECTRICAL AND ELECTRONICS ENGINEERING (ICCEEE), 2013, : 584 - 588
- [2] A Novel FPGA Implementation of AES-128 using Reduced Residue of Prime Numbers based S-Box INTERNATIONAL JOURNAL OF COMPUTER SCIENCE AND NETWORK SECURITY, 2009, 9 (09): : 305 - 309
- [3] Design of an improved method of AES S-box Zhongnan Daxue Xuebao (Ziran Kexue Ban)/Journal of Central South University (Science and Technology), 2007, 38 (02): : 339 - 344
- [4] An Improved VLSI Architecture of S-box for AES Encryption 2013 INTERNATIONAL CONFERENCE ON COMMUNICATION SYSTEMS AND NETWORK TECHNOLOGIES (CSNT 2013), 2013, : 753 - 756
- [5] A New Improved AES S-box with Enhanced Properties INFORMATION SECURITY AND PRIVACY, ACISP 2020, 2020, 12248 : 125 - 141
- [6] AN IMPROVED AES S-BOX AND ITS PERFORMANCE ANALYSIS INTERNATIONAL JOURNAL OF INNOVATIVE COMPUTING INFORMATION AND CONTROL, 2011, 7 (5A): : 2291 - 2302
- [7] An Optimized Implementation of the S-Box using Residues of Prime Numbers INTERNATIONAL JOURNAL OF COMPUTER SCIENCE AND NETWORK SECURITY, 2008, 8 (04): : 304 - 309
- [8] Implementation of AES S-Box Based on VHDL INNOVATIVE COMPUTING AND INFORMATION, ICCIC 2011, PT I, 2011, 231 : 52 - 58
- [9] Improved Truncated Differential Distinguishers of AES with Concrete S-Box PROGRESS IN CRYPTOLOGY, INDOCRYPT 2022, 2022, 13774 : 422 - 445
- [10] Efficient Implementations of S-Box and Inverse S-Box for AES algorithm TENCON 2009 - 2009 IEEE REGION 10 CONFERENCE, VOLS 1-4, 2009, : 2037 - +