A-102-dBm Sensitivity Multichannel Heterodyne Wake-Up Receiver With Integrated ADPLL

被引：0

作者：

Zhang, Linsheng ^{[1
,3
]}

Duvvuri, Divya ^{[2
,3
]}

Bhattacharya, Suprio ^{[3
]}

Dissanayake, Anjana ^{[4
]}

Liu, Xinjian ^{[3
]}

Bishop, Henry L. ^{[5
]}

Zhang, Yaobin ^{[3
]}

Blalock, Travis N. ^{[3
]}

Calhoun, Benton H. ^{[3
]}

Bowers, Steven M. ^{[3
]}

机构：

[1] NXP USA Inc, San Jose, CA 95134 USA

[2] Silicon Labs, Austin, TX 78701 USA

[3] Univ Virginia, Dept Elect & Comp Engn, Charlottesville, VA 22904 USA

[4] CSEM SA, CH-2000 Neuchatel, Switzerland

[5] Amazon com Inc, Redmond, WA 98052 USA

来源：

IEEE OPEN JOURNAL OF THE SOLID-STATE CIRCUITS SOCIETY | 2024年 / 4卷

关键词：

All-digital phase-locked loop (ADPLL); Internet of Things (IoT); low power; receivers; wake-up radios; wake-up receiver (WuRx); PATH; PLL;

D O I：

10.1109/OJSSCS.2024.3387388

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This article presents a binary frequency-shift keying (BFSK) heterodyne wake-up receiver (WuRx) with -102-dBm sensitivity at 2.4 GHz. An integrated low-power all-digital phase-locked loop (ADPLL) allows sharp filtering at the intermediate frequency (IF) to improve sensitivity and interference robustness. The WuRx achieves an average current consumption of 2.2-171 mu A range at 16 s to 0.1-s latency with the packet-level-duty-cycling scheme. In addition, it supports up to 60 channels from 2.300 to 2.536 GHz. A signal-to-interference ratio (SIR) of -27/-30/-46 dB is achieved at 3/5/25-MHz offset from the carrier.

引用

页码：43 / 56

页数：14

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