共 50 条
- [41] Architectural co-synthesis algorithm for distributed, embedded computing systems IEEE Trans Very Large Scale Integr VLSI Syst, 2 (218-229):
- [43] Hardware-software co-synthesis of low power real-time distributed embedded systems with dynamically reconfligurable FPGAs ASP-DAC/VLSI DESIGN 2002: 7TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE AND 15TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS, 2002, : 345 - 352
- [44] A Hybrid Genetic Algorithm for Hardware-Software Synthesis of Heterogeneous Parallel Embedded Systems INFORMATION SYSTEMS ARCHITECTURE AND TECHNOLOGY, PT II, 2018, 656 : 331 - 343
- [45] System level software/hardware partitioning by genetic algorithm Jisuanji Fuzhu Sheji Yu Tuxingxue Xuebao/Journal of Computer-Aided Design and Computer Graphics, 2002, 14 (08): : 731 - 734
- [46] Hardware/Software Co-design Approach for a DCT-Based Watermarking Algorithm 2009 52ND IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2, 2009, : 683 - 686
- [47] CASPER: Concurrent hardware-software co-synthesis of hard real-time aperiodic and periodic specifications of embedded system architectures DESIGN, AUTOMATION AND TEST IN EUROPE, PROCEEDINGS, 1998, : 118 - 124
- [48] A genetic algorithm based approach for multi-objective hardware/software co-optimization (vol 10, pg 36, 2016) SUSTAINABLE COMPUTING-INFORMATICS & SYSTEMS, 2016, 12 : 55 - 55
- [49] SOFTWARE PIPELINING - A GENETIC ALGORITHM APPROACH PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES, 1994, 50 : 311 - 314
- [50] A hybrid genetic algorithm for constrained hardware-software partitioning PROCEEDINGS OF THE 2006 IEEE WORKSHOP ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS AND SYSTEMS, 2006, : 3 - 3