A new hardware implementation of Manchester line decoder

被引：0

作者：

Khorwat, Ibrahim A. ^{[1
,2
]}

Naas, Nabil ^{[1
]}

机构：

[1] Electrical and Electronic Engineering Department, Alfatah University, Libya

[2] Aljeel Aljadeed For Technology Company, Libya

来源：

World Academy of Science, Engineering and Technology | 2010年 / 45卷

关键词：

Timing circuits;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

In this paper, we present a simple circuit for Manchester decoding and without using any complicated or programmable devices. This circuit can decode 90kbps of transmitted encoded data; however, greater than this transmission rate can be decoded if high speed devices were used. We also present a new method for extracting the embedded clock from Manchester data in order to use it for serial-to-parallel conversion. All of our experimental measurements have been done using simulation.

引用

页码：262 / 266

共 50 条

[21] LIGHTWEIGHT HARDWARE IMPLEMENTATION OF VVC TRANSFORM BLOCK FOR ASIC DECODER
Farhat, I
Hamidouche, W.
Grill, A.
Menard, D.
Deforges, O.
2020 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, 2020, : 1663 - 1667
[22] Hardware Implementation of a Real-time Distributed Video Decoder
Yang, Hsin-Ping
Ho, Meng-Hsuan
Hsieh, Hsiao-Chi
Cheng, Po-Hsun
Chen, Sao-Jie
2015 IEEE INTERNATIONAL CONFERENCE ON DIGITAL SIGNAL PROCESSING (DSP), 2015, : 659 - 664
[23] An efficient hardware implementation of MQ decoder of the JPEG2000
Horrigue, Layla
Saidani, Taoufik
Ghodhbani, Refka
Dubois, Julien
Miteran, Johel
Atri, Mohamed
MICROPROCESSORS AND MICROSYSTEMS, 2014, 38 (07) : 659 - 668
[24] Hardware-Accelerated NIOS-II Implementation of a Turbo Decoder
Corneliussen, Andreas
Poulsen, Erik B.
Silpakar, Pradeep
Osteraa, Troels T.
Le Moullec, Yannick
SECOND INTERNATIONAL CONFERENCE ON COMPUTER AND ELECTRICAL ENGINEERING, VOL 1, PROCEEDINGS, 2009, : 367 - +
[25] Real-Time Hardware Implementation of ARM CoreSight Trace Decoder
Zeinolabedin, Seyed Mohammad Ali
Partzsch, Johannes
Mayr, Christian
IEEE DESIGN & TEST, 2021, 38 (01) : 69 - 77
[26] Concurrent Algorithm and Hardware Implementation for Low-Latency Turbo Decoder Using a Single MAP Decoder
Lu, Ya-Cheng
Lu, Erl-Huei
IEICE TRANSACTIONS ON COMMUNICATIONS, 2010, E93B (01) : 1 - 8
[27] Design, hardware implementation and testing of a soft decision information set decoder
McGill Univ, Montreal, Canada
IEEE Trans Educ, 1 (75-82):
[28] Efficient Hardware Accelerator and Implementation of JPEG 2000 MQ Decoder Architecture
Horrigue, Layla
Ghodhbani, Refka
Maqbool, Albia
Abd-Elkawy, Eman H.
Ben Slimane, Jihane
Saidani, Taoufik
Alrslani, Faheed A. F.
Alsuwaylimi, Amjad
Kouki, Marouan
Kachoukh, Amani
ENGINEERING TECHNOLOGY & APPLIED SCIENCE RESEARCH, 2024, 14 (02) : 13463 - 13469
[29] Hardware Implementation of a Latency-Reduced Sphere Decoder With SORN Preprocessing
Baerthel, Moritz
Knobbe, Simon
Rust, Jochen
Paul, Steffen
IEEE ACCESS, 2021, 9 : 91387 - 91401
[30] DESIGN, HARDWARE IMPLEMENTATION AND TESTING OF A SOFT DECISION INFORMATION SET DECODER
KIMPE, M
KNOPP, R
LEIB, H
IEEE TRANSACTIONS ON EDUCATION, 1995, 38 (01) : 75 - 82

← 1 2 3 4 5 →