The hardware design for a genetic algorithm accelerator for packet scheduling problems

被引：0
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作者：
Lee, Yang-Han [1 ]
Jan, Yih-Guang [1 ]
Chou, Yun-Hsih [2 ]
Tseng, Hsien-Wei [1 ]
Chuang, Ming-Hsueh [1 ]
Sheu, Shiann-Tsong [3 ]
Chuang, Yue-Ru [1 ]
Shen, Jei-Jung [1 ]
Fan, Chun-Chieh [4 ]
机构：
[1] Department of Electrical Engineering, Tamkang University, Tamsui, 251, Taiwan
[2] Department of Electronic Engineering, St. John's University, Tamsui, 251, Taiwan
[3] Department of Communication Engineering, National Central University, Taoyuan, 320, Taiwan
[4] Department of Computer and Communication Engineering, St. John's University, Tamsui, 251, Taiwan
来源：
Tamkang Journal of Science and Engineering | 2008年 / 11卷 / 02期
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页码：165 / 174
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