Regular time-efficient VLSI architecture for multiplication modulo 2n+1

被引：0
|
作者：
Zhou, Haohua [1 ]
Li, Zhiyong [1 ]
Xie, Wenlu [1 ]
Zhang, Qianling [1 ]
机构：
[1] Fudan Univ, Shanghai, China
来源：
Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors | 2000年 / 21卷 / 10期
关键词：
Fermat prime - International data encrypt algorithm - Modular multiplication - Multiplication modulo - VLSI architecture;
D O I：
暂无
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学科分类号：
摘要：
(Edited Abstract)
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页码：1032 / 1037
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