Oxide liner, barrier and seed layers, and Cu plating of blind through silicon vias (TSVs) on 300 mm wafers for 3D IC integration

被引：7
|
作者：
Wu, Chien-Ying [1 ]
Chen, Shang-Chun [1 ]
Tzeng, Pei-Jer [1 ]
Lau, John H. [1 ]
Hsu, Yi-Feng [1 ]
Chen, Jui-Chin [1 ]
Hsin, Yu-Chen [1 ]
Chen, Chien-Chou [1 ]
Shen, Shang-Hung [1 ]
Lin, Cha-Hsin [1 ]
Ku, Tzu-Kun [1 ]
Kao, Ming-Jer [1 ]
机构：
[1] Electronics and Optoelectronics Research Laboratories, Industrial Technology Research Institute (ITRI), Chutung, Hsinchu, Taiwan
来源：
Journal of Microelectronics and Electronic Packaging | 2012年 / 9卷 / 01期
关键词：
All Open Access; Bronze;
D O I：
10.4071/imaps.308
中图分类号：
学科分类号：
摘要：
20
引用
收藏
页码：31 / 36
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