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- [1] Package Design for High-Speed SerDes 2010 IEEE ELECTRICAL DESIGN OF ADVANCED PACKAGE & SYSTEMS SYMPOSIUM, 2010,
- [2] High quality factor 5.0 Gbps CTLE circuit for SERDES serial links PROCEEDINGS OF 2018 IEEE EAST-WEST DESIGN & TEST SYMPOSIUM (EWDTS 2018), 2018,
- [3] Hybrid Equalizer Design for 12.5 Gbps Serial Data Transmission ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS, 2009, : 53 - 56
- [4] A Circuit Design Based on high-speed serial communications data transfer network communication interface module PROCEEDINGS OF THE 2016 6TH INTERNATIONAL CONFERENCE ON MACHINERY, MATERIALS, ENVIRONMENT, BIOTECHNOLOGY AND COMPUTER (MMEBC), 2016, 88 : 2053 - 2058
- [5] A novel data processing circuit in high-speed serial communication ASP-DAC 2005: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, 2005, : 1228 - 1231
- [6] A Comma Detection and Word Alignment Circuit for High-speed SerDes 2011 7TH INTERNATIONAL CONFERENCE ON WIRELESS COMMUNICATIONS, NETWORKING AND MOBILE COMPUTING (WICOM), 2011,
- [7] SERIAL DATA ACQUISITION AND SIMULATION FOR A HIGH-SPEED PROTOCOL ANALYZER HEWLETT-PACKARD JOURNAL, 1985, 36 (07): : 18 - 24
- [8] A 12.5Gbps PI-based Quarter-Rate Clock and Data Recovery Circuit with an Adaptive filter of JESD204B Standard 2021 THE 6TH INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUITS AND MICROSYSTEMS (ICICM 2021), 2021, : 5 - 13
- [9] An ASIC Design of a High-Speed Clock and Data Recovery Circuit MEMS, NANO AND SMART SYSTEMS, PTS 1-6, 2012, 403-408 : 1218 - +
- [10] High-speed CRC design for 10 Gbps applications 2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS, 2006, : 3177 - +