Fabrication and electrical characteristics of a trench-type metal-ferroelectric-metal-insulator-semiconductor field effect transistor

We describe a new type of metal-ferroelectric-metal-insulator-semiconductor (MFMIS) memory transistor. This offers a clear advantage in term of device size, and is thus suited for future high-density integration of memory. The MIS transistor of the MFMIS structure is formed along the sidewall of a trench, and the MFM capacitor is formed just over the trench, whereby small device size is realized. We fabricated a test device. The gate insulator in the trench was 14-nm-thick SiO2. In the trench, poly-Si was filled and a 200-nm-thick IrO2 layer was deposited on it. This stack of poly-Si and IrO2 functions as the intermediate metal layer. A 500-nm-thick SrBi2Ta2O9 ferroelectric film was formed by the laser ablation technique. A platinum film was deposited as the top electrode. The drain current-gate voltage characteristics of this test device showed the desired a threshold hysteresis curve whose memory window was about 4.5 V for a voltage swing between -4 V and 8 V.