Interface effects on the characteristics of metal-ferroelectric-insulator-semiconductor field-effect transistor

The interface effects on the electrical characteristics of metal-ferroelectric-insulator-semiconductor field-effect transistor (MFIS-FET) are studied using an improved model in which the expressions for interface and the mobility model are incorporated into Lue model. The interface layer between the ferroelectric and the electrode and the SiO2 layer between the insulator and the semiconductor have been investigated. Capacitance-gate voltage (C-V-G) and drain current-gate voltage (ID-VGS) characteristics are modeled with fixed interface layer and SiO2 layer thicknesses and show good agreement with the experiments, verifying the validity of the improved model and the existence of the interface in the transistor. The characteristics, such as C-V-G, I-D-V-GS and drain current-drain voltage (I-D-V-DS), are modeled respectively with various interface layer and SiO2 layer thicknesses. The thicker the interface layer and SiO2 layer are, the worse the transistor characteristics become. Similar characteristics can be observed at the specific thickness of the two layers, indicating that both interface layer and SiO2 layer should be considered when the characteristics of MFIS-FETs degrade. In addition, the type of the interfaces can be distinguished by comparing the capacitance in the accumulation region. It is expected that this work can offer some useful guidance to the design and performance improvement of MFIS structure devices.