Implementation of Turbo decoder with reduced complexity for spacecraft

Aiming at practical requirements for the received sharply-attenuated weak signal process in space TT&C communication system, an implementation technique of low-complexity Turbo decoder for spacecraft is studied. A modified Turbo decoder structure implemented on FPGA is presented by adopting the Log-MAP algorithm based on approximation by broken line. First, much computation in branch metric of iterative decoding is simplified to save storage resources. Next, a semi-parallel processing is proposed to optimize the whole hardware architecture and raise decoding rate. Through the interleaver and generator matrix recommend by CCSDS, simulation and measured results show that storage process complexity is cut by 29.6% without more slice resources and the coding gain reaches 9.9dB at the BER of 10-6. This decoder has been successfully applied to an aerospace engineering.