1.5 bit substage circuit for charge domain pipelined ADCs

被引：0
|
作者：
Huang, Songren [1 ]
Chen, Zhenhai [1 ,2 ]
Zhang, Hong [3 ]
Li, Xue [3 ]
Qian, Hongwen [2 ]
Yu, Zongguang [1 ,2 ]
机构：
[1] School of Microelectronics, Xidian Univ., Xi'an,710071, China
[2] No. 58 Research Institute, China Electronic Technology Group Corporation, Wuxi,214035, China
[3] School of Electronics and Information Engineering, Xi'an Jiaotong Univ., Xi'an,710049, China
来源：
Xi'an Dianzi Keji Daxue Xuebao/Journal of Xidian University | 2016年 / 43卷 / 06期
关键词：
706.1 Electric Power Systems - 713.1 Amplifiers - 713.4 Pulse Circuits - 716.1 Information Theory and Signal Processing - 802.2 Chemical Reactions;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
14
引用
收藏
页码：170 / 175
相关论文
共 50 条
  • [41] A low power time-interleaved 10-bit 250-MSPS charge domain pipelined ADC for IF sampling
    陈珍海
    钱宏文
    黄嵩人
    张鸿
    于宗光
    Journal of Semiconductors, 2013, (06) : 118 - 125
  • [42] A 10bit 100MS/s pipelined ADC with an improved 1.5bit/stage architecture
    Ye, Fan
    Shi, Yufeng
    Guo, Yao
    Luo, Lei
    Xu, Jun
    Ren, Junyan
    Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors, 2008, 29 (12): : 2359 - 2363
  • [43] A low power time-interleaved 10-bit 250-MSPS charge domain pipelined ADC for IF sampling
    陈珍海
    钱宏文
    黄嵩人
    张鸿
    于宗光
    Journal of Semiconductors, 2013, 34 (06) : 118 - 125
  • [44] A low power time-interleaved 10-bit 250-MSPS charge domain pipelined ADC for IF sampling
    Chen Zhenhai
    Qian Hongwen
    Huang Songren
    Zhang Hong
    Yu Zongguang
    JOURNAL OF SEMICONDUCTORS, 2013, 34 (06)
  • [45] Histogram-Based Calibration of Capacitor Mismatch and Comparator Offset for 1-Bit/Stage Pipelined ADCs
    Huang, Xuan-Lun
    Kang, Ping-Ying
    Yu, Yuan-Chi
    Huang, Jiun-Lang
    JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2011, 27 (04): : 441 - 453
  • [46] Histogram-Based Calibration of Capacitor Mismatch and Comparator Offset for 1-Bit/Stage Pipelined ADCs
    Xuan-Lun Huang
    Ping-Ying Kang
    Yuan-Chi Yu
    Jiun-Lang Huang
    Journal of Electronic Testing, 2011, 27 : 441 - 453
  • [47] A 200-MHz CMOS mixed-mode sample-and-hold circuit for pipelined ADCs
    Jiang, Shan
    Do, Manh Anh
    Yeo, Kiat Seng
    IFIP VLSI-SOC 2006: IFIP WG 10.5 INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION & SYSTEM-ON-CHIP, 2006, : 352 - +
  • [48] Combined radix <2 and 1.5 bit/stage pipelined analogue-to-digital converter
    Nejati, B
    Shoaei, O
    ELECTRONICS LETTERS, 2003, 39 (01) : 2 - 4
  • [49] A 1.5 bit/s Pipelined Analog-to-Digital Converter Design with Independency of Capacitor Mismatch
    李丹
    戎蒙恬
    毛军发
    Journal of Shanghai Jiaotong University, 2007, (04) : 497 - 500
  • [50] The realization of a mismatch-free and 1.5-bit over-sampling pipelined ADC
    Tanaka, S
    Ghoda, Y
    Sugimoto, Y
    2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, : 6194 - 6197
12345