Optimal design of power distribution network for high-speed CMOS circuits

被引：0
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作者：
Formerly Shibaura Institute of Technology, 3-7-5 Toyosu, Koto-ku, Tokyo, Japan [1 ]
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来源：
J. Jpn. Inst. Electron. Packag. | / 5卷 / 337-343期
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All Open Access; Bronze;
D O I：
10.5104/jiep.18.337
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