Development of a High-Linearity Low-Power 24-GHz Low Noise Amplifier

This paper presents a high-linearity low-power 24-GHz CMOS low noise amplifier (LNA). The LNA was designed and implemented using 65 nm RF CMOS technology. The circuit was powered by a 1.2 V supply and operated at a frequency of the 24 GHz. To reduce noise and nonlinearity, an inductor was connected to the gate of the cascode transistor and combined with capacitive cross-coupling. The proposed LNA was fabricated with a maximum OIP3 of 21.8 dBm, lowest power consumption of 6 mW, lowest noise figure of 2.9 dB, and smallest die size of 0.31×0.34 mm2. © ICROS 2022.