Development of a High-Linearity Low-Power 24-GHz Low Noise Amplifier

被引：0

作者：

Choi H.-H. ^{[1
]}

Ryu J.-Y. ^{[1
]}

机构：

[1] Division of Electronics and Communications Engineering, Pukyong National University

来源：

Journal of Institute of Control, Robotics and Systems | 2022年 / 28卷 / 11期

关键词：

24-GHz; 65nm CMOS; high-linearity; low noise amplifier (LNA); low-power;

D O I：

10.5302/J.ICROS.2022.22.0130

中图分类号：

学科分类号：

摘要：

This paper presents a high-linearity low-power 24-GHz CMOS low noise amplifier (LNA). The LNA was designed and implemented using 65 nm RF CMOS technology. The circuit was powered by a 1.2 V supply and operated at a frequency of the 24 GHz. To reduce noise and nonlinearity, an inductor was connected to the gate of the cascode transistor and combined with capacitive cross-coupling. The proposed LNA was fabricated with a maximum OIP3 of 21.8 dBm, lowest power consumption of 6 mW, lowest noise figure of 2.9 dB, and smallest die size of 0.31×0.34 mm2. © ICROS 2022.

引用

页码：1052 / 1057

页数：5

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