A Cycle-Accurate Simulator for a Reconfigurable Multi-Media System

This paper introduces a cycle accurate Simulator for a dynamically REconfigurable MUlti media System called SimREMUS SimREMUS can either be used at transaction level which allows the modeling and simulation of higher level hardware and embedded software or at register transfer level if the dynamic system behavior is desired to be observed at signal level Trade offs among a set of criteria that are frequently used to characterize the design of a reconfigurable computing system such as granularity programmability configurability as well as architecture of processing elements and route modules etc can be quickly evaluated Moreover a complete tool chain for SimREMUS including compiler and debugger is developed SimREMUS could simulate 270k cycles per second for million gates SoC (System on a Chip) and produced one H 264 1080p frame in 15 minutes which might cost days on VCS (platform CPU E5200@ 2 5 Ghz RAM 2 0 GB) Simulation showed that 1080p@30 fps of H 264 High Profile@ Level 4 can be achieved when exploiting a 200 MHz working frequency on the VLSI architecture of REMUS