SMASim: A Cycle-accurate Scalable Multi-core Architecture Simulator

The computer industry has tried to mitigate the problem of achieving computationally more efficient hardware on three fronts: increasing the execution speed by increasing the operating frequency, decreasing the amount of required time to issue a single instruction by enhancing instruction level parallelism (ILP), and increasing the "computational volume" by adding more computational units. Developing complete physical architectures or even experimental FPGA prototypes has turned out to be expensive and to require relatively great amount of resources. Software archtitecture simulators are seen as an efficient way of lowering these costs. SMASim is a software based simulator, motivated by an experimental moving threads architecture that attempts to lower the costs of rapidly designing new architectures. It is based on a general purpose, cycle-accurate event-driven message passing framework between the described hardware architecture elements. Its relatively simple cost model captures the essential properties of many hardware designs. The simulator's design allows easy monitoring of the system and provides execution performance comparable to other cycle-accurate hardware simulators. The focus on SMASim has been to speed up declaring new target architectures with expressive domain specific notations and to decrease the amount of design errors with the static type checker of the implementation language. As a result, the implementation supports modular architecture descriptions on various granularity levels. A graphical user interface is provided to simplify the task of modifying parameters of a simulated system and to provide interactive feedback.