Structure and Principles of Operation of a Quaternion VLSI Multiplier

被引：0

作者：

Cariow, Aleksandr ^{[1
]}

Naumowicz, Mariusz ^{[2
]}

Handkiewicz, Andrzej ^{[3
]}

机构：

[1] West Pomeranian Univ Technol, Fac Comp Sci & Informat Technol, PL-70310 Szczecin, Poland

[2] Poznan Univ Tech, Fac Comp, Ul Piotrowo 3a, PL-60965 Poznan, Poland

[3] Jacob Paradise Univ, Fac Technol, PL-66400 Gorzow Wielkopolski, Poland

来源：

APPLIED SCIENCES-BASEL | 2024年 / 14卷 / 18期

关键词：

hypercomplex numbers; quaternion multiplier; fast algorithm; matrix-vector multiplication; hardware implementation; FPGA; ASIC; SIGNALS;

D O I：

10.3390/app14188123

中图分类号：

O6 [化学];

学科分类号：

0703 ;

摘要：

The paper presents the original structure of a processing unit for multiplying quaternions. The idea of organizing the device is based on the use of fast Hadamard transform blocks. The operation principles of such a device are described. Compared to direct quaternion multiplication, the developed algorithm significantly reduces the number of multiplication and addition operations. Hardware implementations of the developed structure, in FPGA and ASIC, are presented. The FPGA blocks were implemented in the Vivado environment. The ASICs were designed using 130nm technology. The developed scripts in VHDL are available in the GitHub repository.

引用

页数：13

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