Incremental Placement Technology Based on Front-End Design

As the scale and complexity of chips continue to increase, chip design becomes increasingly challenging. Designers typically need multiple iterations to achieve satisfactory results, but the substantial time required for each modification exacerbates the time pressure in the chip design process. Incremental methods are an effective technique to shorten the development iteration time. Therefore, this paper proposes a module-based incremental layout technique utilizing the hierarchical structure of the unflattened netlist. We have developed an incremental EDA tool for mid-version evaluation, covering the process from RTL to placement DEF. This tool enables faster synthesis and layout, assisting designers in assessing the feasibility of the current RTL design, thereby accelerating the estimation of the PPA (Power, Performance, and Area) during version iterations. It aids in making better choices for RTL design and logic synthesis, consequently shortening the chip development iteration time.