A Novel 4H-SiC SGT MOSFET with Improved P plus Shielding Region and Integrated Schottky Barrier Diode

A silicon carbide (SiC) SGT MOSFET featuring a "(sic)"-shaped P+ shielding region (PSR), named SPDT-MOS, is proposed in this article. The improved PSR is introduced as a replacement for the source trench to enhance the forward performance of the device. Its improvement consists of two parts. One is to optimize the electric field distribution of the device, and the other is to expand the current conduction path. Based on the improved PSR and grounded split gate (SG), the device remarkably improves the conduction characteristics, gate oxide reliability, and frequency response. Moreover, the integrated sidewall Schottky barrier diode (SBD) prevents the inherent body diode from being activated and improves the reverse recovery characteristics. As a result, the gate-drain capacitance, gate charge, and reverse recovery charge (Qrr) of the SPDT-MOS are 81.2%, 41.2%, and 90.71% lower than those of the DTMOS, respectively. Compared to the double shielding (DS-MOS), the SPDT-MOS exhibits a 20% reduction in on-resistance and an 8.1% increase in breakdown voltage.