Minimizing Output Capacitance Loss in GaN Power HEMT

Output capacitance (C-OSS) loss (E-DISS) is produced when the C-OSS of a power device undergoes a cycle of charging and discharging, which ideally should be a lossless process. This nonideal phenomenon has been recently revealed to be a critical loss for wide-bandgap devices in high-frequency, soft-switching applications. Despite many studies on its characterizations and physical origins, the reduction of E-DISS, particularly through an approach applicable to circuit application instead of relying on physical device design, has seldom been reported. In this article, we found that the E-DISS of GaN-on-Si high electron mobility transistors (HEMTs) can be significantly reduced by tuning the bias of Si substrate (V-Sub) in dynamic switching. By connecting the substrate to the source or drain via the selected capacitance, V-Sub can be modulated to dynamically follow either the drain-to-source bias (V-DS) or a particular portion of V-DS in switching. Characterizations of a 650 V GaN HEMT with different substrate connections reveal that its E-DISS maximizes at V-Sub = V-DS and minimizes at V-Sub = 0.5V(DS). Compared to the conventional substrate-to-source shorted connection, the E-DISS at V-Sub = 0.5V(DS) is reduced by up to 86%, and the ratio between E-DISS and the stored energy in C-OSS can be reduced from 14.6% to 2.2%. These results unveil a new, easy-to-implement approach to minimize the inherent C-OSS loss of GaN HEMTs in practical applications.