Extending the RISC-V Instruction Set for High Performance Data Compression Hardware Acceleration

With the advent of the big data era, the exponentially growing data processing requirements pose a huge challenge to data compression. Existing FPGA hardware acceleration schemes have many problems and a new hardware acceleration scheme needs to be explored. There are a large number of parallelizable loops in the data compression algorithm, so they can be accelerated by vectorization. In this paper, we improve RISC-V Vector Extension (RVV) for the data compression. We analyze five common compression algorithms and design a class of vector adjacency instructions for vectorization acceleration for hotspot loops in compression algorithms that cannot use RVV vectorization. We design a decoupled vector arithmetic unit for these instructions that is able to complete computations with data-dependent loops in a non-blocking way. The open source vector processor Ara is used to implement our ideas and is synthesized and implemented on the Alveo U50. The results show that our work brings a maximum speedup of 13.24x in cycle count.