A buffer overflow detection and defense method based on RISC-V instruction set extension

被引：0
|
作者：
Chang Liu
Yan-Jun Wu
Jing-Zheng Wu
Chen Zhao
机构：
[1] Chinese Academy of Sciences,Intelligent Software Research Center, Institute of Software
[2] University of Chinese Academy of Sciences,State Key Laboratory of Computer Science, Institute of Software
[3] Chinese Academy of Sciences,undefined
来源：
Cybersecurity | / 6卷
关键词：
RISC-V; Operating system security; Buffer overflow; Control flow hijacking; NX bit; Xibop;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
引用
收藏
相关论文
共 50 条
  • [1] A buffer overflow detection and defense method based on RISC-V instruction set extension
    Liu, Chang
    Wu, Yan-Jun
    Wu, Jing-Zheng
    Zhao, Chen
    CYBERSECURITY, 2023, 6 (01)
  • [2] Audio Denoising Coprocessor Based on RISC-V Custom Instruction Set Extension
    Yuan, Jun
    Zhao, Qiang
    Wang, Wei
    Meng, Xiangsheng
    Li, Jun
    Li, Qin
    ACOUSTICS, 2022, 4 (03): : 538 - 553
  • [3] FlexBex: A RISC-V with a Reconfigurable Instruction Extension
    Nguyen Dao
    Attwood, Andrew
    Healy, Bea
    Koch, Dirk
    2020 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY (ICFPT 2020), 2020, : 190 - 195
  • [4] RISC-VTF: RISC-V Based Extended Instruction Set for Transformer
    Jiao, Qiang
    Hu, Wei
    Liu, Fang
    Dong, Yong
    2021 IEEE INTERNATIONAL CONFERENCE ON SYSTEMS, MAN, AND CYBERNETICS (SMC), 2021, : 1565 - 1570
  • [5] Evaluating RISC-V Vector Instruction Set Architecture Extension with Computer Vision Workloads
    Ruo-Shi Li
    Ping Peng
    Zhi-Yuan Shao
    Hai Jin
    Ran Zheng
    Journal of Computer Science and Technology, 2023, 38 : 807 - 820
  • [6] Bratter: An Instruction Set Extension for Forward Control-Flow Integrity in RISC-V
    Park, Seonghwan
    Kang, Dongwook
    Kang, Jeonghwan
    Kwon, Donghyun
    SENSORS, 2022, 22 (04)
  • [7] RISC-V Instruction Set Architecture Extensions: A Survey
    Cui, Enfang
    Li, Tianzheng
    Wei, Qian
    IEEE ACCESS, 2023, 11 : 24696 - 24711
  • [8] Evaluating RISC-V Vector Instruction Set Architecture Extension with Computer Vision Workloads
    Li, Ruo-Shi
    Peng, Ping
    Shao, Zhi-Yuan
    Jin, Hai
    Zheng, Ran
    JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY, 2023, 38 (04) : 807 - 820
  • [9] Microarchitecture based RISC-V Instruction Set Architecture for Low Power Application
    Deepika, R.
    Priyadharsini, S. M. Gopika
    Malar, M. Muthu
    Anand, I. Vivek
    JOURNAL OF PHARMACEUTICAL NEGATIVE RESULTS, 2022, 13 : 362 - 371
  • [10] The design of scalar aes instruction set extensions for risc-v
    Marshall B.
    Newell G.R.
    Page D.
    Saarinen M.-J.O.
    Wolf C.
    IACR Transactions on Cryptographic Hardware and Embedded Systems, 2020, 2021 (01): : 109 - 136
12345