Threshold voltage in FD-SOI MOSFETs

被引：4

作者：

Pananakakis, Georges ^{[1
]}

Ghibaudo, Gerard ^{[1
]}

Cristoloveanu, Sorin ^{[1
]}

机构：

[1] Univ Grenoble Alpes, IMEP, Grenoble INP, LAHC, 3 Parvis L Neel, F-38016 Grenoble, France

来源：

SOLID-STATE ELECTRONICS | 2024年 / 217卷

关键词：

Threshold voltage; Parameter extraction; MOSFET; FD-SOI; Ultrathin body; ELECTRICAL CHARACTERIZATION; CARRIER MOBILITIES; EXTRACTION; INVERSION; FDSOI; MODEL; GATE; TRANSCONDUCTANCE;

D O I：

10.1016/j.sse.2024.108947

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The threshold voltage definition and measurement in ultrathin FD-SOI MOS transistors are revisited by comparing theoretical and pragmatic extraction techniques, including novel approaches. The respective merits and limitations of methods based on the monitoring of the potential, mobile charge, gate -to -channel capacitance and drain current are emphasized. Back -gate biasing, thickness -induced quantization, potential fluctuations and surface roughness can enhance the disparity between various extraction methods. The origin of these deviations is clarified.

引用

页数：12

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