Technology Development of Wafer-level Ultra-high Density Fan-out (UHDFO) Package

Driven by the rapid development of artificial intelligence, high-performance computing, fanout packaging technology is constantly developing towards fine pitch RDL, multi-layer RDL stacking, high I/O density, and low wafer warpage. UHDFO packaging technology is one of the important choices to solve the above problems. To develop UHDFO packaging technology, we have designed a test vehicle with a package size of 15mm * 15mm, which integrates nine 3.17mm*3.17mm chips with a bump diameter/pitch of 70um/200um respectively. In this work, the four layer stacking RDL 2um/2um process based on the redistribution layer (RDL) first scheme was developed, and the RDL morphology was well controlled; The FC bonding process for wafer reconstruction and electrical interconnection has been developed; The wafer-level underfill process has been developed for filling the bump gaps and buffering stress; The wafer-level molding process for protecting chips and supporting reconstructed wafers has been developed; Laser debonding, release layer cleaning, anti-reflective layer cleaning, and ball planting processes have been successfully developed. We believe that UHDFO packaging technology will play a crucial role in the increasingly prosperous fields of artificial intelligence.