Cascaded Hybrid Fibonacci DC-DC Converter with Interleaved Clock for DC Grid

被引：2
|
作者：
Sai, Toru [1 ]
Liu, Yuhao [1 ]
Sugimoto, Yasuhiro [2 ]
机构：
[1] Tokyo Polytech Univ, Dept Engn, Atsugi, Kanagawa 2430297, Japan
[2] Chuo Univ, Tokyo, Japan
来源：
IEICE ELECTRONICS EXPRESS | 2024年 / 21卷 / 14期
关键词：
key high step-up DC-DC converter; hybrid Fibonacci; interleaved clock; DC grid; HIGH-VOLTAGE-GAIN; STEP-UP CONVERTER; GENERATION; CIRCUITS;
D O I：
10.1587/elex.21.20240233
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A Cascaded hybrid Fibonacci DC-DC converter with interleaved clock for DC grid is proposed. A hybrid Fibonacci stage is connected in series and the interleaved clock is applied. The modified converter is proposed by using two inductors in place of two switches of a typical X3 Fibonacci converter. By this modification, the converter achieved up to 20 of conversion rate (CR) at duty ratio of D = 0.84. The converter consists of two switches, three diodes, and three capacitors for a total of 10 elements. This component count is less than that of the past leading works of the high step-up DC-DC converters. The operation principle was verified using PSIM simulator. A laboratory prototype DC-DC converter achieved CR of 19.5 at D = 0.85.
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页数：6
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