Deep Learning Approach for Modeling the Power Consumption and Delay of Logic Circuits Employing GNRFET Technology

被引:1
|
作者
Emir, Recep [1 ]
Yamacli, Dilek Surekci [2 ]
Yamacli, Serhan [3 ]
Tekin, Sezai Alper [4 ]
机构
[1] Erciyes Univ, Dept Elect & Elect Engn, TR-38039 Kayseri, Turkiye
[2] Izmir Democracy Univ, Dept Econ, TR-35140 Izmir, Turkiye
[3] Izmir Democracy Univ, Dept Biomed Engn, TR-35140 Izmir, Turkiye
[4] Erciyes Univ, Dept Ind Design Engn, TR-38280 Kayseri, Turkiye
关键词
GNRFET; logic design; deep learning; power consumption; delay; DESIGN; ADDER;
D O I
10.3390/electronics13152993
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
The interest in alternative logic technologies is continuously increasing for short nanometer designs. From this viewpoint, logic gates, full adder and D-latch designs based on graphene nanoribbon field effect transistors (GNRFETs) at 7 nm technology nodes were presented, considering that these structures are core elements for digital integrated circuits. Firstly, NOT, NOR and NAND gates were implemented using GNRFETs. Then, 28T full adder and 18T D-latch circuits based on CMOS logic were designed using GNRFETs. As the first result of this work, it was shown through HSPICE simulations that the average power consumption of the considered logic circuits employing GNRFETs was 78.6% lower than those built using classical Si-based MOSFETs. Similarly, the delay advantage of the logic circuits employing GNRFETs was calculated to be 53.2% lower than those using Si-based MOSFET counterparts. In addition, a deep learning model was developed to model both the power consumption and the propagation delay of GNRFET-based logic inverters. As the second result, it was demonstrated that the developed deep learning model could accurately represent the power consumption and delay of GNRFET-based logic circuits with the coefficient of determination (R2) values in the range of 0.86 and 0.99.
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页数:14
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