An efficient Green's function-based Bayesian optimization method for the thermal optimization of multi-chips on a silicon interposer

The escalating adoption of multi -chips configurations in integrated circuits has intensified concerns about power density and heat generation. Inadequate chip layout design can lead to localized overheating, triggering chip component degradation and a decline in module performance. Consequently, proficient thermal design and temperature regulation are crucial. This paper presents a rapid optimization methodology that merges Green ' s function (GF) and Bayesian optimization (BO) to improve the thermal placement optimization of multiple chips on a silicon interposer. An efficient GF method is proposed as a replacement for the time-consuming finite element method (FEM), offering an exhaustive thermal analysis for the entire model. The accuracy of this method is validated through a comparative analysis with FEM, revealing a maximum deviation of less than 0.6% in the steady -state temperature field of the multi -chips model with various chip numbers and chip powers. Notably, GF exhibits a markedly superior computational speed compared to FEM. The GF requires only 0.4 s for a single temperature distribution calculation, making it 60 times faster than the FEM. Subsequently, the analytical solution is combined with the BO algorithm, and its performance is evaluated. The results indicate that, compared to five other optimization algorithms, the BO algorithm can most rapidly find the most ideal optimization layout. The calculation speed of the BO algorithm is 4.5 times faster than the Particle Swarm Optimization algorithm and 4 times faster than the Surrogate Optimization algorithm. The efficiency and accuracy of the proposed GF-based BO approach demonstrates considerable potential in expediting the thermal placement optimization for multichips configurations.