DC-Link Capacitor Current Stress Minimization Strategy for Paralleled Three-Phase Voltage-Source Converters With Interleaving

Interleaving technology in paralleled three-phase voltage-source converters (VSCs) can reduce the dc-link ripple current to improve the power density and lifetime of the dc-link capacitors. However, the carrier-based phase-shifting method commonly used for interleaving cannot achieve the minimum dc-link capacitor current stress, and it is difficult to determine the optimal interleaving angle in real-time control under different operation conditions. The article proposes a modulation strategy to minimize the dc-link capacitor current stress for paralleled VSCs with interleaving under a three-phase balanced load. Unlike the frequency domain analysis method, the effect of interleaving on reducing dc-link ripple current is explored by vector analysis in the time domain. Then, the optimal vector action times are determined based on solving the mathematical model of the linear programming optimization problem, as three degrees of freedom in vector time allocation that can be used for the dc-link current stress optimization exist in interleaved VSCs. The vector sequence suitable for the proposed modulation strategy is selected while considering the circulating current. Finally, analysis and experiments verify that the proposed strategy can reduce dc-link capacitor current stress by about 60% under wide operation conditions compared with the conventional space vector modulation.