Interleaving Modulation Schemes in Asymmetrical Dual Three-Phase Machines for the DC-Link Stress Reduction

The DC-Link capacitor plays a crucial role as far as power density and reliability are concerned: it occupies approximately 40% of the inverter, and causes approximately 30% of its failures. Asymmetrical dual three-phase (ADTP) multiphase arrangements are gaining relevance in the automotive sector for powertrain applications. This work focuses on reducing the impact that the widely used double zero sequence injection (DZSI) family of PWM techniques have on such a bulky and failure-prone component in an ADTP arrangement by means of interleaving techniques. By using the double Fourier integral formalism, the input current spectra and the overall performance of these PWM techniques have been derived, in terms of current rms value and voltage ripple in the DC-Link capacitor. Simulations have shown that choosing an adequate interleaving scheme and angle considerably relieves both current and voltage stresses on the DC-Link capacitor compared to noninterleaved operation. Reductions of 84% current rms and 86% voltage ripple have been achieved at static operating points. Finally, by averaging the rms current over WLTP standard driving cycle, reductions up to 26% have been obtained under more realistic conditions. All this would enhance the reliability and reduce the size of the onboard capacitors in future electric vehicles.