Design of Reading Circuit for High-Reliability 55-nm Split-Gate SuperFlash Technology

The increasing data processing speed and storage volume has urged enhancement in the reliability of flash technology which currently is still the mainstream memory in the embedded field. Despite the process improvement toward the higher-performance flash device, the robustness and reliability of flash reading is also becoming critical which is largely based on the comparison between the cell current and a reference. However, the accuracy of the reference current can be significantly affected by various factors, including location distribution, voltage fluctuation, and stress and temperature effects leading to output error and function failure. In this work, we have designed the reading circuit of 55-nm split-gate SuperFlash for high-reliability applications. Individual memory cells which are partially programmed are selected from the array and are used as current reference cell based on the analysis of cell locations, temperature effects, and so forth. Comparing to the conventional current reference design, our proposed flash reading circuit has exhibited much improved accuracy as well as enhanced endurance and reliability, which can be very instructive for future advanced embedded memory circuit design and optimizations. © 2018 IEEE.