共 50 条
- [31] Investigation on ESD robustness of CMOS devices in a 1.8-v 0.15-μm partially-depleted SOI salicide CMOS technology 2001 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS, PROCEEDINGS OF TECHNICAL PAPERS, 2001, : 41 - 44
- [32] Modeling of single-transistor latch behavior in partially-depleted (PD) SOICMOS devices using a concise SOI-SPICE model SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, VOLS 1 AND 2, PROCEEDINGS, 2001, : 891 - 894
- [37] Efficient Characterization Methodology of Gate-Bulk Leakage and Capacitance for Ultra-Thin Oxide Partially-Depleted (PD) SOI Floating Body CMOS ICMTS 2009: 2009 IEEE INTERNATIONAL CONFERENCE ON MICROELECTRONIC TEST STRUCTURES, 2009, : 133 - 136
- [38] Two-dimensional simulations of the parasitic edge conduction in deep submicron fully depleted SOI NMOS devices. 1997 IEEE INTERNATIONAL SOI CONFERENCE PROCEEDINGS, 1996, : 98 - 99