SYSTOLIC ARRAY IMPLEMENTATION OF ARTIFICIAL NEURAL NETWORKS

被引：6
|
作者：
ASARI, KV
ESWARAN, C
机构：
[1] Department of Electrical Engineering, Indian Institute of Technology, Madras
来源：
MICROPROCESSORS AND MICROSYSTEMS | 1994年 / 18卷 / 08期
关键词：
DIGITAL CIRCUITS; LEARNING RULE; NEURAL NET;
D O I：
10.1016/0141-9331(94)90096-5
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper describes systolic implementation schemes for Hopfield and Hamming nets using completely digital circuits. In the proposed architecture, input data are passed through the neurons on a time share basis, weights are stored in digital shift registers and no separate threshold detectors are used. The architecture provides massive parallelism, reprogrammability and can be expanded by cascading identical chips.
引用
收藏
页码：481 / 488
页数：8
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