Design of half sample delay recursive digital integrators using trapezoidal integration rule

被引:4
|
作者
Jain, Madhu [1 ]
Gupta, Maneesha [2 ]
Jain, N. K. [3 ]
机构
[1] Jaypee Inst Informat Technol, Dept Elect & Commun Engn, A-10,Sect 62, Noida 201307, Uttar Pradesh, India
[2] Netaji Subhas Inst Technol, Div Elect & Commun Engn, Adv Elect Lab, Sect 3, New Delhi 110075, India
[3] Indian Inst Technol, Instrument Design & Dev Ctr, Hauz Khas, New Delhi 110016, India
关键词
digital integrator; trapezoidal integrator; fractional delay filter; linear phase integrator;
D O I
10.1504/IJSISE.2016.075006
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper describes the design of half sample delay recursive digital integrators. For this, a half sample delay is applied on trapezoidal integration rule, then a modified FIR fractional delay filter is used to design recursive digital integrators. The modified FIR fractional delay filter is less complex and more efficient than original one. In this way lower order recursive digital integrators have been designed and compared with existing half sample delay and conventional recursive digital integrators. The results show the effectiveness of the proposed integrators with low percentage absolute magnitude relative error (PARE) and linear phase response over almost 0% to 80% of the entire Nyquist frequency range.
引用
收藏
页码:126 / 134
页数:9
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