MULTICYCLES AND RTL LOGIC SATISFIABILITY

被引:0
|
作者
MILLET, O
机构
关键词
REAL-TIME LOGIC; REAL-TIME SPECIFICATION; SKOLEM FUNCTIONS; RESOLUTION; SAFETY ANALYSIS;
D O I
暂无
中图分类号
TP31 [计算机软件];
学科分类号
081202 ; 0835 ;
摘要
The Jahanian-Mok semidecision procedure for safety analysis of timing properties can be expressed in RTL (Real-Time Logic). We improve this procedure by unifying variables and terms containing a Skolem function. In order to guarantee termination of the potentially infinite process, we introduce the notion of a multicycle, that represents an infinite number of cycles. When the class contains at least one positive cycle, the resolution algorithm operates through the multicycle only a finite number of times. The result is an algorithm that applies to a larger class of there exists for-all-formulas and operates with the same efficiency as the Jahanian-Mok procedure.
引用
收藏
页码:73 / 86
页数:14
相关论文
共 50 条
  • [1] LPSAT: A unified approach to RTL satisfiability
    Zeng, ZH
    Kalla, P
    Ciesielski, M
    DESIGN, AUTOMATION AND TEST IN EUROPE, CONFERENCE AND EXHIBITION 2001, PROCEEDINGS, 2001, : 398 - 402
  • [2] Multiplexer model for RTL satisfiability using MILP
    Navarro, H
    Montiel-Nelson, JA
    Sosa, J
    García, JC
    Fay, DQM
    ELECTRONICS LETTERS, 2004, 40 (07) : 417 - 418
  • [3] RTSAT: A hybrid satisfiability solver for RTL circuits
    Deng, Shujun
    Wu, Weimin
    Bian, Jinian
    2006 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS PROCEEDINGS, VOLS 1-4: VOL 1: SIGNAL PROCESSING, 2006, : 2429 - 2433
  • [4] RTL satisfiability solving using an ATPG based approach
    Chen, MC
    Wu, WM
    Bian, JN
    2005 6TH INTERNATIONAL CONFERENCE ON ASIC PROCEEDINGS, BOOKS 1 AND 2, 2005, : 910 - 913
  • [5] Satisfiability -: Algorithms and logic
    Pudlák, P
    MATHEMATICAL FOUNDATIONS OF COMPUTER SCIENCE 1998, 1998, 1450 : 129 - 141
  • [6] Accelerated verification of RTL assertions based on satisfiability solvers
    Fraer, R
    Ikram, S
    Kamhi, G
    Leonard, T
    Mokkedem, A
    SEVENTH IEEE INTERNATIONAL HIGH-LEVEL DESIGN VALIDATION AND TEST WORKSHOP, PROCEEDINGS, 2002, : 107 - 110
  • [7] Logic programming with satisfiability
    Codish, Michael
    Lagoon, Vitaly
    Stuckey, Peter J.
    THEORY AND PRACTICE OF LOGIC PROGRAMMING, 2008, 8 (01) : 121 - 128
  • [8] EHSAT: An efficient RTL satisfiability solver using an extended DPLL procedure
    Deng, Shujun
    Bian, Jinian
    Wu, Weimin
    Yang, Xiaoqing
    Zhao, Yanni
    2007 44TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, 2007, : 588 - +
  • [9] RTL Test Generation via Fault Insertion and Hybrid Satisfiability Solving
    Wu, Weimin
    PROCEEDINGS OF THE 11TH JOINT CONFERENCE ON INFORMATION SCIENCES, 2008,
  • [10] RTL estimation of steering logic power
    Anton, C
    Bogliolo, A
    Civera, P
    Colonescu, I
    Macii, E
    Poncino, M
    INTEGRATED CIRCUIT DESIGN, PROCEEDINGS: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION, 2000, 1918 : 36 - 46