A FERROELECTRIC DRAM CELL FOR HIGH-DENSITY NVRAMS

被引:58
|
作者
MOAZZAMI, R [1 ]
HU, CM [1 ]
SHEPHERD, WH [1 ]
机构
[1] NATL SEMICOND CORP,SANTA CLARA,CA 95052
关键词
D O I
10.1109/55.62994
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The operation of a ferroelectric DRAM cell for nonvolatile RAM (NVRAM) applications is described. Because polarization reversal only occurs during nonvolatile store /recall operations but not during read/write operations, ferroelectric fatigue is not a serious endurance problem. For a 3-V power supply, the worst-case effective silicon dioxide thickness of the unoptimized lead zirconate titanate film studied here is less than 17 Å. This cell can be the basis of a very high-density NVRAM with practically no read/write cycle limit and at least 1010 nonvolatile store/recall cycles. © 1990 IEEE
引用
收藏
页码:454 / 456
页数:3
相关论文
共 50 条
  • [1] A high-density DRAM cell with built-in gain stage
    Kamoulakos, G
    Tsiatouhas, Y
    Chrisanthopoulos, A
    Arapoyanni, A
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2001, 48 (06) : 1194 - 1199
  • [2] High-Density DRAM Package Simulation
    Wan, Ng Hong
    [J]. PROCEEDINGS OF THE 2012 IEEE 14TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE, 2012, : 700 - 704
  • [3] AN EXPERIMENTAL HIGH-DENSITY DRAM CELL WITH A BUILT-IN GAIN STAGE
    KIM, W
    KIH, J
    KIM, G
    JUNG, S
    AHN, G
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1994, 29 (08) : 978 - 981
  • [4] Exploring and Optimizing Chipkill-correct for Persistent Memory Based on High-density NVRAMs
    Zhang, Da
    Sridharan, Vilas
    Jian, Xun
    [J]. 2018 51ST ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE (MICRO), 2018, : 710 - 723
  • [5] Low-damage gate etching with high degree of anisotropy in high-density DRAM cell
    Kim, IG
    Kim, NS
    Park, JS
    Park, DY
    [J]. JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 2002, 41 (4B): : 2380 - 2384
  • [6] A 70NS HIGH-DENSITY CMOS DRAM
    CHWANG, R
    CHOI, M
    CREEK, D
    STERN, S
    PELLEY, P
    SCHUTZ, J
    BOHR, M
    WARKENTIN, P
    YU, K
    [J]. ISSCC DIGEST OF TECHNICAL PAPERS, 1983, 26 : 56 - &
  • [7] Highly scalable saddle MOSFET for high-density and high-performance DRAM
    Park, KH
    Han, K
    Lee, JH
    [J]. IEEE ELECTRON DEVICE LETTERS, 2005, 26 (09) : 690 - 692
  • [8] High-Density NVMe SSD With DRAM-Less eRAID Architecture
    Luo, Jianjun
    Liu, Hailuan
    He, Ying
    Vargas-Rosales, Cesar
    Fan, Lingyan
    [J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2023, 31 (11) : 1865 - 1869
  • [9] A 3D packaging technology for high-density stacked DRAM
    Kawano, Masaya
    [J]. 2007 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATIONS (VLSI-TSA), PROCEEDINGS OF TECHNICAL PAPERS, 2007, : 62 - 63
  • [10] Proposal of a logic compatible merged-type gain cell for high-density embedded DRAM's
    Mukai, M
    Hayashi, Y
    Komatsu, Y
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1999, 46 (06) : 1201 - 1206