FPGA design and hardware implementation of a convolutional neural network for classification of saccadic eye movements

被引：0

作者：

Cano, Carlos ^{[1
]}

Stoean, Ruxandra ^{[2
]}

Joya, Gonzalo ^{[1
]}

机构：

[1] Univ Malaga, Dept Tecnol Elect, ETSI Telecomunicac, Campus Teatinos, E-29071 Malaga, Spain

[2] Univ Craiova, Fac Sci, Dept Comp Sci, 13 AI Cuza St, Craiova 200585, Romania

来源：

ANNALS OF THE UNIVERSITY OF CRAIOVA-MATHEMATICS AND COMPUTER SCIENCE SERIES | 2018年 / 45卷 / 02期

关键词：

Field programmable gate arrays (FPGA); Convolutional Neural Network (CNN); Saccade classification; Hardware optimization; High-level Synthesis (HLS); Algorithm design and analysis;

D O I：

暂无

中图分类号：

O1 [数学];

学科分类号：

0701 ; 070101 ;

摘要：

The paper presents an efficient design and implementation of a convolutional neural network on an FPGA device. The aim is not only theoretical but also practical, since the solution will be used in a medical clinic dealing with SpinoCerebellar Ataxia type 2 as part of a larger project. Hence, the current work targets both high learning capabilities as well as portability. The former has been tackled through the apppointment a convolutional neural network while the latter is concerned with the hardware implementation of the complex network on a FPGA. The preliminary results encourage the further exploitation of the proposed solution.

引用

页码：263 / 274

页数：12

共 50 条

[21] Transformation of sensory signals into commands for saccadic eye movements: a neural network study
Liu, L
Sun, HJ
Guo, A
[J]. JOURNAL OF THEORETICAL BIOLOGY, 1997, 189 (02) : 121 - 131
[22] Hardware Implementation of Convolutional Neural Network for Face Feature Extraction
Ding, Ru
Tian, Xuemei
Bai, Guoqiang
Su, Guangda
Wu, Xingjun
[J]. 2019 IEEE 13TH INTERNATIONAL CONFERENCE ON ASIC (ASICON), 2019,
[23] Data and Hardware Efficient Design for Convolutional Neural Network
Lin, Yue-Jin
Chang, Tian Sheuan
[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2018, 65 (05) : 1642 - 1651
[24] All Binarized Convolutional Neural Network and Its implementation on an FPGA
Shimoda, Masayuki
Sato, Shimpei
Nakahara, Hiroki
[J]. 2017 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE TECHNOLOGY (ICFPT), 2017, : 291 - 294
[25] Efficient FPGA Implementation of Local Binary Convolutional Neural Network
Zhakatayev, Aidyn
Lee, Jongeun
[J]. 24TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC 2019), 2019, : 699 - 704
[26] Optimizing OpenCL Implementation of Deep Convolutional Neural Network on FPGA
Qiao, Yuran
Shen, Junzhong
Huang, Dafei
Yang, Qianming
Wen, Mei
Zhang, Chunyuan
[J]. NETWORK AND PARALLEL COMPUTING (NPC 2017), 2017, 10578 : 100 - 111
[27] FPGA Implementation of Convolutional Neural Network Based on Stochastic Computing
Kim, Daewoo
Moghaddam, Mansureh S.
Moradian, Hossein
Sim, Hyeonuk
Lee, Jongeun
Choi, Kiyoung
[J]. 2017 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE TECHNOLOGY (ICFPT), 2017, : 287 - 290
[28] Digital hardware implementation of a neural network used for classification
Faiedh, H
Gafsi, Z
Torki, K
Besbes, K
[J]. 16TH INTERNATIONAL CONFERENCE ON MICROELECTRONICS, PROCEEDINGS, 2004, : 551 - 554
[29] Spiking Neural Network Implementation on FPGA for Multiclass Classification
Zhang, Jin
Zhang, Lei
[J]. 2023 IEEE INTERNATIONAL SYSTEMS CONFERENCE, SYSCON, 2023,
[30] A Neural Model for the Adaptive Control of Saccadic Eye Movements
Saeb, Sohrab
Weber, Cornelius
Triesch, Jochen
[J]. IJCNN: 2009 INTERNATIONAL JOINT CONFERENCE ON NEURAL NETWORKS, VOLS 1- 6, 2009, : 2083 - 2090

← 1 2 3 4 5 →