INALAS/INGAAS/INP HEMTS WITH HIGH BREAKDOWN VOLTAGES USING DOUBLE-RECESS GATE PROCESS

被引:28
|
作者
BOOS, JB [1 ]
KRUPPA, W [1 ]
机构
[1] SFA INC,LANDOVER,MD 20785
关键词
TRANSISTORS; SEMICONDUCTOR DEVICES AND MATERIALS;
D O I
10.1049/el:19911185
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The DC and RF performance of InAlAs/InGaAs/InP HEMTs fabricated using a double-recess gate process are reported. A gate-drain breakdown voltage as high as 16 V was observed. The HEMTs also exhibited a high source-drain breakdown voltage near pinchoff of 16 V and a low RF output conductance of 6 mS/mm. For a 1.4-mu-m gate length, an intrinsic transconductance or 560 mS/mm and f(T) and f(max) values of 16 and 40 GHz, respectively, were achieved.
引用
下载
收藏
页码:1909 / 1910
页数:2
相关论文
共 50 条
  • [21] Analysis of issues in gate recess etching in the InAlAs/InGaAs HEMT manufacturing process
    Min, Byoung-Gue
    Lee, Jong-Min
    Yoon, Hyung Sup
    Chang, Woo-Jin
    Park, Jong-Yul
    Kang, Dong Min
    Chang, Sung-Jae
    Jung, Hyun-Wook
    ETRI JOURNAL, 2023, 45 (01) : 171 - 179
  • [22] Double-recess structure with an InP passivation layer for 0.1-μm-gate InPHEMTs
    Kitabayashi, H
    Sugitani, S
    Fukai, YK
    Yamane, Y
    Enoki, T
    IEICE TRANSACTIONS ON ELECTRONICS, 2003, E86C (10): : 2000 - 2003
  • [23] INALAS/INGAAS/INP MODFETS WITH UNIFORM THRESHOLD VOLTAGE OBTAINED BY SELECTIVE WET GATE RECESS
    TONG, M
    NUMMILA, K
    KETTERSON, A
    ADESIDA, I
    CANEAU, C
    BHAT, R
    IEEE ELECTRON DEVICE LETTERS, 1992, 13 (10) : 525 - 527
  • [24] Selective gate recess RIE etching by CHF3+BCl3 in InAlAs/InGaAs HEMTs
    Kao, HC
    Lai, LS
    Chan, YJ
    1997 INTERNATIONAL CONFERENCE ON INDIUM PHOSPHIDE AND RELATED MATERIALS - CONFERENCE PROCEEDINGS, 1997, : 137 - 140
  • [25] Degradation mechanism and reliability improvement of InGaAs/InAlAs/InP HEMTs using new gate metal electrode technology
    Chou, YC
    Grundbacher, R
    Leung, D
    Lai, R
    Kan, Q
    Eng, D
    Liu, PH
    Block, T
    Oki, A
    2005 INTERNATIONAL CONFERENCE ON INDIUM PHOSPHIDE AND RELATED MATERIALS, 2005, : 223 - 226
  • [26] 0.1-mu m InAlAs/InGaAs HEMTS with an InP-recess-etch stopper grown by MOCVD
    Enoki, T
    Ito, H
    Ikuta, K
    Umeda, Y
    Ishii, Y
    MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, 1996, 11 (03) : 135 - 139
  • [27] 30-nm-gate InAlAs/InGaAs HEMTs lattice-matched to InP substrates
    Suemitsu, T
    Ishii, T
    Yokoyama, H
    Umeda, Y
    Enoki, T
    Ishii, Y
    Tamamura, T
    INTERNATIONAL ELECTRON DEVICES MEETING 1998 - TECHNICAL DIGEST, 1998, : 223 - 226
  • [28] Two-step gate-recess process combining selective wet-etching and digital wet-etching for InAlAs/InGaAs InP-based HEMTs
    Zhong, Ying-hui
    Sun, Shu-xiang
    Wong, Wen-bin
    Wang, Hai-li
    Liu, Xiao-ming
    Duan, Zhi-yong
    Ding, Peng
    Jin, Zhi
    FRONTIERS OF INFORMATION TECHNOLOGY & ELECTRONIC ENGINEERING, 2017, 18 (08) : 1180 - 1185
  • [29] Self-consistent analysis of double-δ-doped InAlAs/InGaAs/InP HEMTs
    Li Dong-Lin
    Zeng Yi-Ping
    CHINESE PHYSICS, 2006, 15 (11): : 2735 - 2741
  • [30] Two-step gate-recess process combining selective wet-etching and digital wet-etching for InAlAs/InGaAs InP-based HEMTs
    Ying-hui Zhong
    Shu-xiang Sun
    Wen-bin Wong
    Hai-li Wang
    Xiao-ming Liu
    Zhi-yong Duan
    Peng Ding
    Zhi Jin
    Frontiers of Information Technology & Electronic Engineering, 2017, 18 : 1180 - 1185