DELAY-TIME ANALYSIS FOR SHORT GATE-LENGTH GAAS-MESFETS

被引:7
|
作者
NUMMILA, K
KETTERSON, AA
ADESIDA, I
机构
[1] UNIV ILLINOIS,CTR COMPOUND SEMICOND MICROELECTR,COORDINATED SCI LAB,URBANA,IL 61801
[2] UNIV ILLINOIS,DEPT ELECT & COMP ENGN,URBANA,IL 61801
基金
美国国家科学基金会;
关键词
D O I
10.1016/0038-1101(94)00097-Y
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
GaAs MESFETs with gate lengths from 55 to 150 nm have been fabricated and characterized. By using selective etching for the gate recess, the channel thickness as well as the aspect ratio of the devices of each gate length are known accurately. A cutoff frequency as high as 112 GHz was obtained for a 100 nm x 150 mu m device. To study the intrinsic characteristics of these devices, the effects of the pad and the substrate parasitics were first measured and corrected for. Two independent methods adopted to perform this correction have been compared with both resulting in the same intrinsic delay times. Delay time analysis was used to determine the transit time of the electrons in the channel, the channel charging delay, and the drain delay, all as functions of gate length. The results show that the high speed performance of devices with ultra-small gate lengths is limited by the pad parasitics and the intrinsic channel charging and drain delay.
引用
收藏
页码:517 / 524
页数:8
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